Reinaldo A. Bergamaschi, Raul Camposano, et al.
Integration, the VLSI Journal
Paper
Observable time windows: Verifying high-level synthesis results
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Related
Conference paper
Redesign using state splitting
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Reinaldo A. Bergamaschi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reinaldo A. Bergamaschi, Andreas Kuehlmann
IEEE Transactions on VLSI Systems