Conference paper
State-based power analysis for systems-on-chip
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003
Paper
Observable time windows: Verifying high-level synthesis results
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
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EDAC 1990
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Conference paper
Early and accurate analysis of SoCs: Oxymoron or real?
Reinaldo A. Bergamaschi
SLIP 2004