Shaojie Wang, Sharad Malik, et al.
DATE 2003
Paper
Observable time windows: Verifying high-level synthesis results
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Related
Reinaldo A. Bergamaschi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hiren D. Patel, Sandeep K. Shukla, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, et al.
IEEE Design and Test of Computers