Conference paper
State-based power analysis for systems-on-chip
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Hiren D. Patel, Sandeep K. Shukla, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reinaldo A. Bergamaschi
SLIP 2004