Publication
IEEE JSSC
Paper

Multiple Word/Bit Line Redundancy for Semiconductor Memories

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Abstract

Multiple word/bit line redundancy techniques at the chip level are shown to be powerful enough to obtain good yields for chips with much higher rates of faults/chip than without redundancy. This is possible because, in many instances, chips which are rejected as being bad still have a high percentage of usable bits on them. The redundancy techniques described consist of putting spare decoders and spare word and bit lines on a chip in order to be able to replace defective lines of the chip with good lines while still maintaining the same address. Based on a first-pass design of a 16K chip, a significant improvement in the number of usable bits per wafer appears possible. The leverage for improvement is shown to be strongly dependent upon the type of cell, the layout, and the technology used. Copyright © 1978 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1978

Publication

IEEE JSSC

Authors

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