Publication
ICCAD 1989
Conference paper
Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout
Abstract
A method is presented for floorplanning data-path chips by a technique of multiterrain partitioning with integrated global wiring to partition the objects into terrains, followed by multistack placement and standard-cell placement. Requirements on terrain size, terrain shape, wirability, and timing are considered. Results obtained for some chip designs are presented.