Multi-purpose VLSI chip for adaptive data compression of bilevel images

Abstract

A VLSI chip for data compression has been implemented based on a general-purpose adaptive binary arithmetic coding (ABAC) architecture. The architecture permits the reuse of adapter and arithmetic coder logic in a universal way, which together with application -specific model logic can create a variety of powerful compression systems. The specific version of the adapter/coder used is the 'Q-Coder'. The hardware implementation is in a single HCMOS chip, to maximize speed and minimize cost. The primary purpose of the chip is to provide superior data compression performance for bilevel image data by using conditional binary source models together with adaptive arithmetic coding. The coding scheme implemented is called the Adaptive Bilevel Image Compression (ABIC) algorithm. On business documents, it outperforms such nonadaptive algorithms as the CCITT Group 4 (T.6) Standard and comes into its own when adapting to documents scanned at different resolutions or which include significantly different data such as digital halftones.