Conference paper
Optimal shielding/spacing metrics for low power design
Ravishankar Arunachalam, Emrah Acar, et al.
ISVLSI 2003
Power grids for sub-micron large integrated circuits are performance limiting factors due to the large power dissipated (e.g. 100 W at 1.8 V). The analysis of such power grids is important in order to predict and possibly improve the performance. Current classical analysis methods are falling behind as grids become ever larger. This paper proposes a new efficient analysis method suitable for both DC and transient simulation of large power grids.
Ravishankar Arunachalam, Emrah Acar, et al.
ISVLSI 2003
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ICECS 2001
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