MOSFET's with Polysilicon Gates Self-Aligned to the Field Isolation and to the Source and Drain Regions

The fabrication procedure and device characteristics of MOSFET's having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the Fet. An-other novel feature of this “recessed-gate” device is a self-registering electrical connection between the gate and the metallic interconnection pattern. Compared to MOSFET's fabricated using more conventional methods, smaller FET's with increased packing density result from this misregistration-tolerant contacting technique and the doubly self-aligned gate electrode structure. The new FET structure may be ap-plied to various integrated circuits such as ROM’s, PLA’s, and dynamic RAM's. The use of a second layer of polysilicon and The addition of a fifth masking operation yields a dynamic RAM cell of small area with a diffused storage region. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.