Mega-challenges for nano-silicon technology

Abstract

Silicon technology with gate dimensions of a few tens of nanometers is already in mass production. With continued innovation and advancements in materials, lithography tools, and device structures, further scaling down to sub-ten nanometer gate length is planned over the next 10 years. Continued silicon technology scaling faces many challenges, two of the most important being growing standby power dissipation and increasing variability in device characteristics. These effects are frequently cited as the reasons why Moore's Law is "broken", or why silicon technology scaling is coming to an end, and why entirely new types of nanotechnology will be needed for higher performance computing architectures in the future. Actually these issues are the embodiments of silicon technology's approach to atomistic and quantum-mechanical physics boundaries. These same challenges must be met by nano devices in order to be competitive with Silicon technology on a power/performance/cost basis. This talk will describe the power and variabilty challenges facing silicon technology, in order to set some of the metrics by which nanotechnology can compete with silicon for highperformance logic applications. © 2006 IEEE.