Conference paper
Hierarchical global wiring for custom chip design
W.K. Luk, D.T. Tang, et al.
DAC 1986
The problem considered here is that of permuting the pins of modules in order to maximize the number of connections which can be achieved in the polysilicon level. Using a graph-theoretic formulation, the problem is shown to be equivalent to that of removing fewest edges in a certain graph to break all cycles. The problem is proved to be NP-complete. A heuristic based on branch-and-bound is proposed. © 1984.
W.K. Luk, D.T. Tang, et al.
DAC 1986
C. Chiang, C.K. Wong, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A. Albrecht, S.K. Cheung, et al.
Journal of Computational Physics
P.C. Yue, C.K. Wong
International Journal of Computer & Information Sciences