About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEE TC
Paper
Mathematical “Lower Bounds” and the Logic Circuit Designer
Abstract
The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder. © 1970, IEEE. All rights reserved.