Publication
IEEE Transactions on Magnetics
Paper

Major-minor loop, single-level-masking bubble chip

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Abstract

A major-minor loop chip design is presented which requires one high resolution masking step and no critical mask alignments. This design may therefore be implemented with electron- beam, X-ray, or deep-UV conformable-contact lithography to define the submicron linewidths required in ultra-high density devices. Chips with 20-μm period were fabricated with a layered Au-first, NiFe-second structure in a design which provided 6 percent overall margins; substitution of an improved merge component would allow a 10 percent margin overlap of all functions. Tests of components with 8μm periods show margins of similar percentage values. Current requirements for the devices are low (10 mA for 8 μm period) so that the designs appear extendable to much higher densities. Copyright © 1978 by The Institute of Electrical and Flectronics Engineers, Inc.

Date

01 Jan 1978

Publication

IEEE Transactions on Magnetics

Authors

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