MAISE: An interconnect simulation engine for timing and noise analysis

Abstract

This paper describes MAISE, an embedded linear circuit simulator for use mainly within timing and noise analysis tools. MAISE achieves the fastest possible analysis performance over a wide range of circuit sizes and topologies by an adaptive architecture that allows applying the most efficient combination of model reduction algorithms and linear solvers for each class of circuits. The main pillar of adaptability in MAISE is a novel nodal-analysis formulation (PNA) which permits the use of symmetric, positive-definite Cholesky solvers for all circuit topologies. Moreover, frequently occurring special cases, e.g., inductor-resistor tree structures result in particular types of matrices that are solved by an even faster linear time algorithm. Model order reduction algorithms employed in MAISE exploit symmetry and positive-definiteness whenever available and use symmetric-Lanczos iteration and nonstandard inner-products for generating the Krylov subspace basis. The efficiency of the new simulator is supported by a wide range of industrial examples. © 2008 IEEE.