The paper examines the assumption that asperites and corners in electrodes can be preferential sites for electrical breakdown of silicon dioxide capacitors. It was assumed for this purpose that asperities can be approximated by spherical surfaces, and the breakdown voltage was then calculated at such asperities. Calculations showed that the breakdown voltage of a planar silicon dioxide capacitor can be lowered by one half to two thirds by asperities, when their radius is less than about one half of the oxide thickness. Such a decrease in the breakdown voltage is widely observed in polysilicon oxide capacitors. The effect of asperities is alleviated by a trapped electron charge, which can increase the breakdown voltage significantly. The spherical asperity model accounted for the breakdown voltages observed on a wide range of polysilicon oxide capacitors with oxide thickness varying from 45 to 820 nm. The radius of asperities responsible for breakdown in these experiments was roughly estimated 25-35 nm. © 1983.