Low power sampling latch for up to 25 Gb/s 2× oversampling CDR in 90-nm CMOS

Abstract

A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10 -12 is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a small area of 30×20 μm 2. © 2006 IEEE.