Publication
IEEE JSSC
Paper

Loop Decoder for Josephson Memory Arrays

View publication

Abstract

A detailed theoretical and experimental investigation is presented. concerning a novel so-called “loop decoder” using Josephson interferometers as the active elements. Successful operation of a dc powered, full 3-bit decoder is demonstrated with large operating margins. Addressing time is measured to be 180 ps and decoding time per stage is measured to be 30 ps. Excellent agreement is obtained between the experiments and computer simulations, thus establishing that present Josephson circuit models are reasonably accurate and well understood. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

Date

Publication

IEEE JSSC

Authors

Share