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IEEE Transactions on VLSI Systems
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L1-L2 interconnect design methodology and arbitration in 3-D IC multicore compute clusters

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Abstract

We introduce a novel 3-D implementation of the interconnect between cores and shared L2 cache banks for multicore clusters. The 3-D structure extends cluster sizes that can be supported with tolerable wire delays. As a result of the shorter connections achieved by splitting existing 2-D design into four layers, performance is improved and area and power are reduced. The splitting enables implementation of a better arbitration scheme, which leads to additional performance improvement.

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IEEE Transactions on VLSI Systems

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