Des Autom Embedded Syst

Interlanguage communication synthesis for heterogeneous specifications

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Nowadays the design of complex systems requires the cooperation of several teams belonging to different cultures and using different languages. It is necessary to dispose of new design and verification methods to handle multilanguage approaches. This paper presents an approach for the interlanguage communication synthesis of heterogeneous specifications. The system is represented by a set of interconnected subsystems specified in different languages with different concepts, different interface types, different communication schemes and some of them can even be IP modules. The subsystems exchange data through abstract communication channels. The objective is to refine the abstract communication channels into an implementation. The result is a set of interconnected processors communicating through signals, buses and dedicated components. An example illustrates the usefulness of this approach for the design of an adaptive speed control system that was described in SDL and Matlab.