Conference paper
Inductance analysis of on-chip interconnects
Sandip Kundu, Uttam Ghoshal
EDTC 1997
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
Sandip Kundu, Uttam Ghoshal
EDTC 1997
Reinaldo A. Bergamaschi, D. Brand, et al.
ICCAD 1995
Sandip Kundu
ISIT 1990
Viktors Berstis, D. Brand, et al.
ISCAS 1984