D. Brand
ACM SIGPLAN Notices
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
D. Brand
ACM SIGPLAN Notices
D. Brand, Reinaldo A. Bergamaschi, et al.
ICCAD 1995
R. Thomas, Sandip Kundu
European Conference on Design Automation 1992
Sandip Kundu
IEICE Transactions on Information and Systems