How to process a multi million gate ASIC layout in 21 hours

Abstract

This paper discusses the turn around time reduction issue for the ASIC layout design process. It reviews key technologies to reduce the runtime of several of the most time consuming design steps. It also introduces a flexible yet easy to use reference layout design flow called FastTAT that is implemented in TheGuide, an IBM ASIC design methodology tool. The layout of a 17 million gate design has been processed within 21 hours from unplaced netlist to a fully routed and timing optimized design. Practical design issues related to turn around time are also discussed. © 2007 IEEE.