Publication
IEEE TC
Paper

High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm

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Abstract

This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion. Copyright © 1970 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1970

Publication

IEEE TC

Authors

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