Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the 81-86 GHz band was designed and fabricated in 0.13 μm SiGe technology. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chip achieves maximum gain of 73 dB, 6 dB noise figure, better than -12 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chip includes a power amplifier (PA), image-reject driver, variable RF attenuators, IF-to-RF upconverting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 16.6 dBm, Psat of 18.8 dBm on a single-ended output and consumes 1.8 W.