Chemically vapor deposited (CVD) Si rich SiO2 layers on thermal or CVD SiO2 layers incorporated into metal-insulator-semiconductor (MIS) capacitor structures are shown to give very large injected electron currents at low to moderate negative gate voltage biases. The dependence of this injection mechanism on the Si rich SiO2 composition and thickness, temperature, capacitor area, annealing conditions, gate metal (Al or Au), and underlying SiO2 thickness is described. Photocurrent measurements are discussed and are shown to give similar barrier energies as seen for "uniform" internal photoemission into SiO2. From the experimental electrical and photoelectrical measurements described here and transmission electron microscopy (TEM) and Auger studies of others, a possible model to explain this phenomenon based on electric field distortion caused by a two phase mixture of amorphous Si and SiO2 is presented. Two experimental applications of these structures are described. In one application, an electrically alterable read-only memory structure is fabricated, and it is shown to operate at lower voltage (?13 V) and power than popular commercially available devices. The other application involves a "multilayer" structure with alternating layers of polycrystalline Si islands (20 or 40 Å in diameter) and CVD SiO2 deposited on thermal SiO 2 incorporated into an MIS capacitor which also gives large injected electron currents at moderate negative gate voltages similar to the currents observed with Si rich SiO2. This latter experimental application lends credibility to the proposed two phase model.