Hierarchical system synchronization and signaling for high-performance - Low-latency interconnects

Abstract

We address a hierarchical synchronization distribution architecture for high-performance and low-latency operations. Furthermore, the bandwidth overhead is minimized, and the accuracy can be adjusted to the application. A novel signaling channel with an open, user-extendable protocol is proposed. An approximation method to estimate system-wide clock jitter is introduced and applied to the Optical Shared MemOry Supercomputer Interconnects System (OSMOSIS). First measurement results, which reveal the challenges of future system synchronization requirements and the potential of the defined architecture, are presented.