About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Paper
Hardware implementation of fair queuing algorithms for asynchronous transfer mode networks
Abstract
Providing quality-of-service guarantees in both cell- and packet-based networks requires the use of a scheduling algorithm in the switches and network interfaces. These algorithms need to be implemented in hardware in a high-speed switch. In this article the author present a number of approaches to implement scheduling algorithms in hardware. The authors begin by presenting a general methodology for the design of timestamp-based fair queuing algorithms that provide the same bounds on end-to-end delay and fairness as those of Weighted Fair Queuing, yet have efficient hardware implementations. Based on this general methodology, the authors describe two specific agorithms, Framed Fair Queuing and Starting Potential-Based Fair Queuing, and discuss illustrative implementations in hardware. These algorithms may be used in both cell switches and packet switches with variable-size packets. A methodology for combining a traffic shaper with this class of fair queuing schedulers is also presented for use in network interface devices, such as an ATM segmentation and reassembly device.
Related
Workshop paper
pyp2pcluster: A cluster discovery tool
Conference paper