High-k gate dielectrics such as HfO2 and metal gates such as TiN have been deployed across a wide range of silicon-based CMOS logic products. In some gate-first technologies, SiGe channels (cSiGe) have been implemented simultaneously for threshold voltage control in p-channel metal-oxide-semiconductor fieldeffect transistors (pMOSFET). Herein, we review aspects related to the impact of high-k/channel interfacial layers on Si, SiGe, and IIIV gate stack quality and device performance. First, we review remote oxygen scavenging approaches for interfacial SiO2 thinning in HfO2/Si nFET and HfO2/cSiGe pFET devices. We show that they allow equivalent oxide thickness (EOT) to be reduced to 0.4- 0.5 nm, and we discuss device performance and reliability tradeoffs that may limit continued EOT scaling. For later technology nodes, high-carrier-mobility III-V semiconductors channels such as InGaAs are under consideration. We summarize three high-k/InGaAs channel interface approaches: Direct high-k deposition, Si capping, and InP capping.