Fast estimation of area-delay trade-offs in circuit sizing

Abstract

Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13% correct comparisons), with an average error of 5.76% in the area differences predicted. © 2005 IEEE.