EXPERIMENTAL TECHNOLOGY AND CHARACTERIZATION OF SELF-ALIGNED 0. 1 mu M-GATE-LENGTH LOW-TEMPERATURE OPERATION NMOS DEVICES.

Abstract

Results are presented from work aimed at demonstrating the feasibility of a Si FET technology in the 0. 1- mu m-gate-length regime. Self-aligned, n-channel polysilicon gated MOSFETs were designed for optimum operation at cryogenic temperatures (77 degree K) with reduced power-supply levels. A variety of test chips were assembled and several wafers processed. Direct-write electron-beam lithography was used to pattern all levels. The shortest devices fabricated had gate lengths of 70 nm. Measured device characteristics yielded over 750-mS/mm transconductance.