We measure the role of structural defects, including grain boundaries and step edges, in determining the electrical transport characteristics of polycrystalline graphene monolayers synthesized on C-face SiC(0 0 0 1 ) by thermal decomposition. A combination of multi-probe scanning tunneling microscopy/potentiometry and low-energy electron microscopy allows the transport properties of individual grain boundaries to be correlated with their misorientation and atomic-level structure, without any device fabrication. We find that different types of grain boundary show dramatically different transport properties, and that boundaries can change structure and resistivity along their length. Boundary regions made up of dislocation superlattices separated by continuous graphene exhibit relatively low resistivity which is comparable to the resistivity of the graphene sheet itself. Other grain boundaries display trench structures with a resistivity 1-2 orders of magnitude greater and sufficient to dominate transport through the polycrystalline sheet. We also measure the transport properties of step edges and monolayer-bilayer boundaries on C-face graphene and compare them to Si-face graphene. Such measurements offer a guideline for optimizing graphene growth on SiC to improve its electronic properties.