Efficient integer implementations for faster linear transforms

Higher throughput requirements in image processing systems require faster implementations of the underlying transforms. A new architecture for efficient implementations of linear, orthogonal transforms is discussed, with specific examples developed for the 2-D DCT in image compression. It is shown that the methods described in this paper can provide lower real estate usage in FPGAs by as much as 3-4x, as well as reduction in execution cycles by about 30% on a range of embedded processors where more clock cycles are required for multiplication than for addition.