K. Ismail, B.S. Meyerson, et al.
Surface Science
An optimized Si/SiGe heterostructure for complementary metal-oxide-semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si0.7Ge0.3 buffer, a strained Si quantum well (the electron channel), and a strained Si1-xGex (0.7 > x > 0.5) quantum well (the hole channel). The channel charge distribution is predicted using 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-μm channel length generation. © 1996 IEEE.
K. Ismail, B.S. Meyerson, et al.
Surface Science
S.J. Koester, K. Ismail, et al.
DRC 1997
K. Ismail, S. Washburn, et al.
Applied Physics Letters
K. Ismail, S. Nelson, et al.
Applied Physics Letters