Publication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper

Design of Multioutput CMOS Combinational Logic Circuits for Robust Testability

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Abstract

Circuit delays and timing skews in input changes influence the choice of tests to detect transistor stuck-open faults in static CMOS circuits. Tests that detect transistor stuck-open faults independent of the delays in the circuit under test are called robust tests. Robust tests may not exist for all transistor stuck-open faults in CMOS circuits. This problem may be redressed if care is taken at the time of design. Earlier a robust testable design was proposed for single output functions based on primitive gates that could meet any fan-in constraint. It is known that parity gates such as Exclusive-OR or Exclusive-NOR require the same amount of area as primitive gates (NANDor NOR)I. n this paper we propose a testable design for multioutput functions using parity gates that will always produce a realization with robust tests. The use of parity gates allows more logic sharing among various outputs than would have been possible otherwise. © 1989 IEEE

Date

01 Jan 1989

Publication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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