Design and implementation of the POWER5™ microprocessor

Abstract

The design and implementation of the POWER™, the next generation of IBM's POWER microprocessors were discussed. It was shown that this design sets a latest standard of server performance by incorporating simultaneous multithreading (SMT). The detailed analysis of workload simulation, power grid characteristics and macro-level power ensured adequate decoupling for induced noise. It was found that the exact duration of intensity and mechanism of each response is fully programmable. It also provides timely and flexible protection for 1-64w systems while minimizing performance impact because the throttling response requires no software or service processor intervention.