Critical path identification and delay tests of dynamic circuits

Abstract

Dynamic circuit families are commonly used to achieve high operating speeds in recent microprocessor designs. Because of their noise sensitivity, it is necessary to design dynamic circuits accurately to achieve performance goals and avoid problems with noise. Although individual cells can be analyzed effectively, timing verification of the entire design is not easy because of the increased complexity. In this paper, we develop a new approach to find critical paths and generate test vectors for delay test of large dynamic circuits, given information on the path delays of the unit cells. We introduce the concept of 'path gates' to represent the discharge paths in a dynamic circuit, and have developed an extraction tool (PEAR) to construct the path gates. The critical path analyzer (CRITIC) is used to identify the critical paths and generate delay tests for the integrated units. The technique has been successfully applied to industry circuits.