Phosphorous diffused and arsenic ion-implanted p-n junctions have been prepared in 0.5- and 2-Ω cm p-type 〈100〉 Si wafers. Leakage currents have been measured on gated diode structures of various geometries as a function of bias voltage and temperature. From these measurements the relative importance of the surface, depletion layer, and bulk carrier generation to junction leakage have been determined. The leakage current levels measured on the ion-implanted junctions are comparable to those measured on the diffused junctions. The surface generation leakage component is the largest, ranging from 5×10-15-10-13 A/mil2 at 25 °C. This sufficiently large to dominate the leakage current for junctions with areas less than approximately 103 mil2. The depletion-layer generation current IDB is much smaller than would be expected. It is only comparable to the diffusion current at 25 °C where IDB?IDIFF?10-16 A/mil2 for defect-free junctions. IDIFF becomes the largest for large-area diodes or for junctions of any area at higher temperatures. The dependence of the leakage current on junction reverse bias and gate bias voltage is stronger than would be predicted for growth in the depletion-layer thickness with bias. We observe IL∼Vn with n∼1-2. This enhanced leakage occurs at the junction perimeter and is associated with increased perimeter electric fields.