Circuit Analysis, Logic Simulation, and Design Verification for VLSI

Abstract

ln this paper, we consider computer-aided design techniques for VLSI. Specifically, the areas of circuit analysis, logic simulation and design verification are discussed with an emphasis on time domain techniques. Recently, researchers have concentrated on two general problem areas. One important problem discussed is the efficient, exact-time analysis of large-scale circuits. The other area is the unification of these techniques with logic simulation and design verification technique in so called multimode or multilevel systems. Copyright © 1983 by The Institute of Electrical and Electronics Engineers, Inc.