About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
Solid-State Electronics
Paper
Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology
Abstract
We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON-OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source-drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance-voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects. © 2002 Elsevier Science Ltd. All rights reserved.