Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays

Abstract

In this paper we discuss parametric measurements of devices implemented in a commercial 14nm CMOS FinFET process taken at cryogenic temperatures. The data may be used to create cryo-CMOS device models for developing CMOS control and readout circuits of qubits in quantum computer. Access to a large number of devices was enabled using an integrated digitally addressable analog multiplexer; the combination of this multiplexer and the set of devices accessible through the multiplexer forms an addressable parametric array. We will discuss the test structure, the measurement technique, the test challenges, and the device parameter shifts that we have observed, over a temperature range from 300K down to 7.9K. The addressable nature of the multiplexer allows investigation of a variety of device types in a single sample cool down. In addition, the accessibility of large numbers of devices allows statistics to be gathered on the variation of key device parameter spreads with temperature.