A 1.0-µm CMOS technology with three layers of metal is used to implement a high-density master image that contains logic and RAM’s. The image allows the use of more than 1 000 000 transistors. A hierarchical design methodology is described. This chip offers variable-sized physical partitions and RAM macros. No fixed area sizes and locations for partitions and macros are necessary. Density and performance of custom chips are approached by the described methodology with significantly lower development cost and time. Copyright © 1987 by The Institute of Electrical and Electronics, Inc.