In recent years, an increasing number of papers have focused on the cell selection problem. However, previous papers fail to consider the actual problems of performing cell selection in the after placement and CTS optimization stages of in- dustrial designs. This paper discusses the obstacles found when applying state-of-the-art Lagrangian relaxation-based cell selection in a real industrial ow. Solutions to such obstacles are presented, filling the gap in previous literature. We propose a new method to find a suitable set of initial Lagrange multipliers based on the initial gates sizes in the netlist. Fast convergence in the presence of small timing violations is achieved by a novel Lagrange multiplier update method. Our new timing-constrained formulation incorporates and balances both power and area as optimization objectives. We also present a ranking method to reduce sign-off timer calls that gives a 10x speed up in the cell selection process. Experimental results show quality improvements on a set of already deeply timing, power and area-optimized high-performance industrial microprocessor blocks with very tight constraints. Leakage power reduction of up to 18.2% is achieved (10.8% total and 7.2% on average), while timing, area and dynamic power are also improved.