About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
EOS/ESD 2007
Conference paper
Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies
Abstract
S-parameter test structures show total capacitances per perimeter of ESD diodes increased from ∼0.42fF/μm in 90nm technologies to ∼0.7fF/μm in 65nm and 45nm technologies. To achieve lower capacitances for high frequency circuits, layout and process optimization are needed. SCR devices from a 45nm technology show ∼0.32fF/μm and can be used for circuit applications with stringent capacitance requirement. Two different BEOL wiring schemes are investigated for optimized metal coupling capacitance.