Area-efficient architectures for the Viterbi algorithm

Abstract

An architecture model for area-efficient implementation of the Viterbi algorithm is described. The authors present a systematic way of partitioning and scheduling N trellis states into P add-compare-selects (N > P), which are connected by a fixed-interconnection or a multistage-interconnection network. The proposed architecture allows pipelining to increase the throughput rate even when the channel has memory or intersymbol interference. Design strategies of path metric storage are also discussed. Favorable results are presented for trellises of de Bruijn graphs and matched-spectral-null (MSN) trellis codes.