Analytical modeling of multithreaded pipeline performance

Abstract

The throughput of pipelined processors suffers due to delays associated with instruction dependencies and memory latencies. Multithreaded architectures try to tolerate such delays by sharing the pipeline with independent instruction threads. This paper proposes an analytic model which is used to quantitate the advantage of multithreaded architectures. The analytic model provides an exact solution, which is significantly better than bounds obtainable from simpler approximate techniques. Unlike previous analytic models of such systems, the model presented here accepts a general distribution for the interlock delays with multiple latencies. The model provides a much quicker performance estimate than simulation. The model has been validated for a variety of input distributions using previously published simulation-based results.