Analytical Comparison of 3-Level 2-Phase and Double-Step-Down Topologies for Integrated High-Ratio DC-DC Converters in BCD and GaN Process

Abstract

This paper provides a comprehensive analysis and comparison between 3-level and double-step-down (DSD) integrated power converters, which are two of the most popular topologies for 48V-to-1V point-of-load conversion. Because DSD converters have two inductors, the 3-level topology in this study is also constructed with 2-phase interleaved operation (3L2P) to make the comparison fair. Same chip-area budget, loading conditions and ripples are also ensured, such that comparisons are made under similar bill-of-materials and power density to provide engineers a more practical view of the characteristics of both topologies. Theoretical analysis is provided with similarity in switching behaviors discovered. Transistor-level simulations are conducted in a 180-nm BCD and a commercially available enhancement-mode GaN processes, assuming all power FETs are integrated on-chip. The simulation results agree with our analysis. In conclusion, DSD converters can achieve an overall higher efficiency than 3-level converters at near-same conditions with same or smaller chip-area budget due to the much lower conduction loss. In addition, both topologies, especially the DSD, achieved significantly higher (up to 12%) efficiency in a 200-V GaN process compared to a 55-V BCD process despite being overrated (due to limited available options), because of the much lower switching loss. This makes GaN process worth considering for integrated high-ratio DC-DC converter designs even though the current fabrication cost will be higher.