The conventional method to evaluate switching loss of power MOSFETs is commonly based on the existence of the plateau gate-voltage region in the gate-charge plot. However, a very different behavior of the MOSFET with disappearance of the plateau region is observed under significant current diversion between channel and parasitic capacitances when a large gate drive current is applied to turn off the MOSFET. As the modern power converter is pursuing higher switching frequency, the gate drive current becomes larger accordingly to turn on and off the power MOSFET faster. Hence, this paper proposes an analytical model to predict the timing pattern and the switching loss more precisely in such conditions. Simulation and measurement have been conducted to validate this model, showing an accurate estimate of the switching loss at fast switching transition and a good match with the conventional model at slow switching transition. Moreover, non-linearity of the MOSFET's output capacitance is considered in this model, suggesting a handy graphical method to determine the timing pattern and the switching loss properly in practice.