An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability

Abstract

We present algorithm and IP design of a parallel Reed-Solomon decoder with up to 8-byte random error correcting capability. The decoder soft-IP consists of a core that can be designed as parallel combinational circuits of around 62K primitive gates and a peripheral that can be arranged flexibly depending on codeword configurations. The technology mapping results with even commercial FPGA demonstrates that a single core can achieve a throughput well over 40 Gbps when it is 4-stage pipelined. A single decoder design can process N-interleaved codewords efficiently if the core is operated in a time division multiplexing manner.