Publication
IEEE JSSC
Paper

An Experimental 64-Bit Decoded Josephson NDRO Random Access Memory

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Abstract

The design and testing of an experimental fully decoded 64-bit Josephson NDRO random access memory chip are described. Tree decoders were used to access the memory cells. The basic memory cell was a ring cell containing a single write gate. The chips were built in a coarse 25 μm technology since neither speed nor density were stressed in this study. an access time of 4 ns with full margins and of 2.3 ns with reduced margins were demonstrated. The corresponding full memory cycle times were 5 and 3.5 ns, respectively. Good agreement with computer simulations was obtained throughout. Copyright © 1978 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1978

Publication

IEEE JSSC

Authors

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