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Publication
DATE 2008
Conference paper
An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation
Abstract
An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated to reflect the spatial correlation. The proposed method is practical for chip-level extraction task, and the experiments on full-path extraction exhibit its high accuracy and efficiency. © 2008 EDAA.