Babak Soltanian, Herschel Ainspan, et al.
CICC 2006
A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-μm 25-GHz BiCMOS. A Δ Σ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip ΔΣ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-N synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of -88 dBc/Hz for 2.47-GHz output frequency and -98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply.
Babak Soltanian, Herschel Ainspan, et al.
CICC 2006
Woogeun Rhee, Herschel Ainspan, et al.
CICC 2003
Keith A. Jenkins, Woogeun Rhee, et al.
SiRF 2006
John F. Bulzacchelli, Mounir Meghelli, et al.
IEEE Journal of Solid-State Circuits