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Publication
IEEE Transactions on VLSI Systems
Paper
Accurate area and delay estimation from RTL descriptions
Abstract
In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design. The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-fit polynomial area and delay models on the resulting technology-independent representation. The estimation techniques were incorporated into a tool called QUEST. QUEST was used by designers of a large commercial CPU to obtain quick feedback on the area and delay impact of behavioral modifications, resulting in significant savings in design schedule. © 1998 IEEE.