About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Conference paper
A scalable, digital BIST circuit for measurement and compensation of static phase offset
Abstract
An on-chip circuit to measure static phase offset between a reference signal and the feedback signal of a PLL (phase-locked loop) is designed using only digital elements. It is demonstrated in a 65 nm, 1.0 V CMOS technology. It has a measured resolution of 2ps and a range of more than +/- 100ps of phase offset and, and consumes 3mW of power at 1 GHz. It uses an on-chip calibration referred to the reference clock frequency. The measured results are reported through digital scan chains. © 2009 IEEE.