The increased performance and circuit/bit densities of today':s semiconductor chips require corresponding technological advancements in chip packaging. More interconnections and increased heat dissipation must be accommodated in a package compatible with the higher performance of these chips. In the packaging approach described, increased package performance and reliability were achieved by the use of a multilayered ceramic substrate upon which nine chips can be mounted. Conductors for ground, signal, and power lines are interlayered in the ceramic with connections to the top surfaces and to pins at the bottom surface for connection to external circuitry. This multilayer multichip module significantly advances the state of the art; it provides higher circuit density and performance with a ten-fold increase in circuit density over previous logic systems hardware. © 1980 IEEE.